This invention relates to a buffer memory arrangement for use in supplying data to or receiving data from a plurality of peripheral devices, subsystem components, or the like.
Buffer memories are used to buffer or temporarily store data that is to be transferred between components or subsystems of a system. Buffer memories may be employed in a variety of arrangements, for example, to buffer data transferred between subsystems of a data processing system, to buffer data transferred between peripheral units and a central processor of a data processing system, or in general to buffer data transferred between any elements of a data processing system.
Peripheral devices, subsystems, etc., typically gain access to a buffer memory of a system by one of two methods. In a first method, a central processing unit regularly polls the peripheral devices and/or subsystems in the course of carrying out its processing function to determine if a request for access is present. If it is, that request for access is treated as an "interrupt" and, if higher priority interrupts are not present, the central processing unit will branch or jump to a particular location in the instruction stream where the memory address of a desired service routine for servicing the request is located or generated. Polling offers the advantage of permitting very simple peripheral device design because most of the so-called intelligence or logic remains in the central processing unit. On the other hand, polling presents the disadvantage of delaying the servicing of a peripheral device request for access since the device must first be polled, and then it may even have to wait to be serviced.
A second method for gaining access to a buffer memory is the so-called direct memory access method. Here, peripheral devices and/or subsystems are allowed to interrupt the central processing unit without having to wait to be polled. Thus, inefficiencies of waiting which are associated with the polling method are eliminated but more complexity in the form of intelligence and logic must be designed into the peripheral devices so that the devices "know" what is wanted of the buffer memory (whether to write data into or read data from the memory) and the location or address in buffer memory where the operation is to take place.